Area-Efficient AES Design for IoT Devices

Abstract

This project prioritizes both low power consumption and space efficiency while improving AES implementation for Internet of Things devices with limited resources. Clock gating methods and the integration of the Sub-Bytes function into the State Register greatly minimize power consumption and area overhead by lowering the number of clock cycles that are allocated to inactive circuit parts. This solution provides notable reductions in area overhead over traditional AES implementations through careful hardware design decisions and algorithmic optimization. This work makes a substantial contribution to the development of effective and safe cryptographic systems designed to meet the unique requirements of IoT settings, where security is of utmost importance yet resources are scarce.